A reversible processor architecture and its reversible logic design

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.

All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.
Original languageEnglish
Title of host publicationReversible Computation : Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers
EditorsAlexis De Vos, Robert Wille
Number of pages13
PublisherSpringer
Publication date2012
Pages30-42
ISBN (Print)978-3-642-29516-4
ISBN (Electronic)978-3-642-29517-1
DOIs
Publication statusPublished - 2012
Event3rd International Workshop on Reversible Computation - Gent, Belgium
Duration: 4 Jul 20115 Jul 2011
Conference number: 3

Conference

Conference3rd International Workshop on Reversible Computation
Nummer3
LandBelgium
ByGent
Periode04/07/201105/07/2011
SeriesLecture notes in computer science
Volume7165
ISSN0302-9743

ID: 34263110